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 ICS556-01
BROADCOM 25 MHZ LVDS CLOCK
Description
The ICS556-01 is a clock oscillator with LVDS outputs. Using a standard 25 MHz crystal, the device outputs a .25 mHz (reference) differential output clock. The operation voltage is 2.5 V to support today's popular interfaces. The termination resistor is off-chip.
Features
* * * * * *
Packaged in 8-pin TSSOP Requires no external components Low Phase Jitter: <1 ps from 10 kHz to 10 MHz Differential LVDS outputs Operating voltage of 2.5 V. Advanced, low power, sub-micron CMOS process
Block Diagram
VDD OE
X1 25 MHz Crystal X2 Crystal Oscillator
CLK 100 CLK
2
GND
MDS 556-01 B I n t e gra te d C i r c u i t S y s t e m s
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525 Race Stre et, San Jo se, CA 9 5126
Revision 020204 te l (40 8) 2 97-12 01
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ICS556-01 Broadcom 25 MHz LVDS Clock
Pin Assignment
X1 VDD GND GND
1 2 3 4 8 7 6 5
X2 OE CLK CLK
ICS556-01 8 Pin (173m il) TSSO P or SO IC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
X1 VDD GND GND CLK CLK OE X2
Pin Type
Input Power Power Power Output Power Input Input Crystal connection.
Pin Description
Power supply. Connect to 2.5 V. Connect to ground. Connect to ground. Inverting differential clock output. Differential clock output. Output Enable. Internal pull-up resistor. Crystal connection. only partial outputs are used, it is recommended to terminate the un-used outputs.
External Component Selection
The ICS556-01 requires a minimum number of external components for proper operation. A 100 termination resistor between CLK and CLK is provided on-chip.
2.5V LVDS_Driver
2.5V + -
Decoupling Capacitors
A decoupling capacitor of 0.01F should be connected between VDD and GND on pins 2 and 3 as close to the ICS556-01 as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
R1 100 ohm
100 Ohm Differential Transmission Line
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
MDS 556-01 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 020204 tel (4 08) 297-1 201
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ICS556-01 Broadcom 25 MHz LVDS Clock
Quartz Crystal
The ICS556-01 25 MHz LVDS Clock utilizes an external crystal to generate a low phase noise output. To assure the best system performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The frequency of oscillation of a quartz crystal is determined by its "cut" and by the load capacitors connected to it. The crystal specified for use with the ICS556-01 is designed to have zero frequency error when the total of on-chip plus stray capacitance is 5 pF.
Recommended Crystal Parameters: Initial Accuracy of 25C20 ppm Temperature Stability20 ppm Load Capacitance5 pf Shunt Capacitance, C02 pF Max Equivalent Series Resistance80 Max The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS556-01. There should be no via's between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. The value (in pF) of these crystal caps should equal (CL - 12 pF)*2. In this equation, CL =crystal load capacitance in pF. Example: or a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS556-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Reference crystal parameters
Min.
0 +2.375
Typ.
Max.
+70 +2.625
Units
C V
Refer to page 3
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ICS556-01 Broadcom 25 MHz LVDS Clock
DC Electrical Characteristics
VDD=2.5 V 5% , Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Output High Voltage Output Low Voltage Output High Voltage (CMOS Level) Operating Supply Current
Symbol
VDD VOH VOL VOH IDD
Conditions
Note 1 Note 1 IOH = -4 mA No load, OE = 1 No load, OE = 0
Min.
2.375 1.375
Typ.
Max.
2.625 1.125
Units
V V V V
VDD-0.4 5.3 1.7
mA mA
Note 1: Outputs terminated with 50 to VDD/2
AC Electrical Characteristics
VDD = 2.5 V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise
Parameter
Input Frequency Output Frequency Differential Output Voltages (VOD) VOD Offset Voltage (VOS) VOS Differential Output Short Circuit Current (IOSD) Output Short Circuit Current (IOS) Output Rise Time Output Fall Time Output Clock Duty Cycle Maximum Output Jitter (p-p) Phase Jitter (RMS)
Conditions
Min.
Typ.
25 25
Max. Units
MHz MHz 450 40 1.375 25 mV mV V mV mA mA 1.2 1.2 55 ns ns % ps 2.5 ps
250 VOD Magnitude Change VOS Magnitude Change -40 1.125
350 0 1.25 3 -3.5 -3.5
20% to 80%, no load 20% to 80%, no load Measured at 1.25 V, CL=5 pF CL=5 pF Phase Noise integrated from 10 kHz to 10 MHz 45
0.8 0.8 50 40 1.8
MDS 556-01 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS556-01 Broadcom 25 MHz LVDS Clock
Parameter Measurement Information
V DD = 2.5V5%
Z = 50
SCOPE
Qx
50 LVDS Z = 50
nQx
80%
80%
VOD
50
Clock Outputs
20% tOR tOF
20%
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT RISE/FALL TIME
V DD
nCLK
LV D S
out
D C In p u t
50 50
out
CLK Pulse Width
V O S / V O S
tPERIOD
VOS SETUP
tPW & tPERIOD
V DD
nCLK
VOH
out
CLK t()
VOL
DC Input
LVDS
100
V OD / V OD
out
tjit() = t() - t()mean = Phase Jitter
PHASE JITTER
V OD SETUP
VDD nCLK CLK VOD Cross Points VOS
GND
DIFFERENTIAL INPUT LEVEL
MDS 556-01 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 020204 tel (4 08) 297-1 201
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ICS556-01 Broadcom 25 MHz LVDS Clock
Package Outline and Package Dimensions (8-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters Symbol Min Max
Inches Min Max
E1 IN D EX AR EA
E
1
2
D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 0.004
A 2 A 1
A
c
-Ce
b S E A T IN G P LA N E L
aaa
C
Ordering Information
Part / Order Number
ICS556G-01 ICS556G-01T
Marking
556G-01 556G-01
Shipping packaging
Tubes Tape and Reel
Package
8-pin TSSOP 8-pin TSSOP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 556-01 B In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
Revision 020204 tel (4 08) 297-1 201
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